Examples described herein relate generally to signal paths in memory. Examples of methods and apparatuses are described for controlling the locking of a delay locked loop in a timing path when a memory clock changes frequency (e.g. when a memory is placed in gear down mode).
Memory, such as dynamic random access memory (DRAM), is used in a multitude of electronics systems (e.g., portable computers, desktop computers, server systems, mobile devices, etc.) and has gone through several advancements over the years. For example, double data rate DRAM (DDRAM) was a first progression from the initial DRAM and operates at double the rate. Since then, DDRAM has also gone through a series of development milestones with each milestone improving the performance. This progression of development resulted in sequentially numbered DDRAM, e.g. DDR2, DDR3, and DDR4 development iterations. The DDR4 iteration has introduced new operating modes due to the ever increasing clock speeds of current computing systems employing DDR memories.
One of the new modes being discussed is a gear down mode. The gear down mode may be used when the DDR4 memory is included in a system that is generally running at a very high clock frequency. Gear down mode may at least involve the DDR4 memory reducing the internal clock rate of operation, e.g., divide the clock by two, which may allow for reduced power consumption and relaxed internal timing constraints. The command to gear down may be received at any time and the DDR4's timing circuit may experience some issues when gearing down in various situations. For example, a delay locked loop (DDL) may have trouble staying locked, e.g., keeping the output clock signal remaining in phase with the input clock signal, when converting to a reduced internal clock rate. Additionally, a latency of a forward path may need to be adjusted based on the new internal clock, rate of the DDR4 memory while in the gear down mode.